Buried plated cell architecture for modern DRAMs (64 Mbit and higher) is one of the most promising concepts for improvements in memory technology. As is widely known, a DRAM cell is formed from a transistor and a capacitor. In a buried plate cell, a buried layer of a doped semiconductor material is formed in a substrate beneath the top source of the DRAM. This buried layer substantially forms one of the capacitor plates of the memory cell. The second capacitor plate is formed within a trench cell adjacent to the buried layer. The trench cell is filled with a doped semiconductor such as polysilicon which forms the second plate of the capacitor. The trench fill material is electrically isolated from the buried layer by means of a dielectric layer surrounding the trench.
An example of a prior art DRAM cell with a buried plate trench cell architecture is shown in FIG. 1. A p channel field effect transistor 15 includes an n+ drainwell 11, n+ source well 12 and p- channel region 13, which has gate 14 disposed thereon. Buried layer 16, here shown doped n+, is disposed within a p- doped substrate 17 beneath the active regions of transistor 15. A trench 31 filled with n+ doped polysilicon 54, 56 penetrates the buried layer 16. A thin dielectric layer 19, typically an oxide layer, surrounds the trench 31 in order to electrically isolate the trench-fill n+ material from the buried layer region 16. In this manner, a trench capacitor 27 is formed in which the n+ polysilicon within trench 31 forms one plate of capacitor 27. Note that buried region 16 has a portion adjacent to the trench region 31. Channel region 13 also has a portion which is adjacent to trench region 31. These adjacent portions of buried region 16 and channel region 13 form the other plate of trench capacitor 27. Dielectric layer 19 thus separates the two plates of trench capacitor 27. The drain well 11 is electrically connected to the trench cell 31 via trench electrode 41. Logic level voltages are thus transferred from the transistor 15 to the trench capacitor 27 which stores the voltage data.
From the structure of FIG. 1, one can ascertain that a vertical parasitic transistor 18 is created between the buried layer 16 and the drain well 11. N+ buried layer 16 acts as the source, p- region 13 acts like the channel region, and n+ well 11 acts as the drain of the parasitic transistor 18. Doped polysilicon 56 acts as the gate, and isolation collar 51 acts as the insulator between the gate and the channel of parasitic transistor 18. The parasitic device 18 must be kept turned off when the trench electrode 41 is at a high logic level voltage. This is accomplished by conveniently forming the isolation collar 51 as a thick oxide or the like, and having it extend down the trench 31 to substantially isolate the adjoining portion of channel region 13 from the doped polysilicon 56.
In a typical trench cell process, the trench 31 is first filled with doped semiconductor material 54 up until a predetermined level near the bottom of the isolation collar 51. This level is indicated by the cross-sectional depth line 29 in FIG. 1. After the first fill, the isolation collar 51 is formed, which may be a thick oxide layer such as tetra-ethyl-ortho-silicate (TEOS). The trench 31 is then filled with another "plug" 56 of the same doped semiconductor material from line 29 to the top surface. Thus, in order to incorporate the benefits of a thick isolation collar, two "plugs" of n+ polysilicon or similar material are needed to fill the trench 31.
Other examples of prior art DRAM trench cells which have isolation collars are described in U.S. Pat. No. 4,794,434 entitled "Trench Cell for a DRAM", issued on Dec. 27, 1985 to P. Pefley III. This patent discloses trench cells filled with either n+ or p+ polysilicon and describes a technique for raising the potential of the buried layer in order to reduce the maximum voltage which will be developed across the insulating layer.
The oxide isolation collar technique, while affording a number of advantages, suffers from several drawbacks in the course of subsequent processing. One problem is that subsequent high temperature steps will diffuse oxygen through top layers and eventually through the collar. This will lead to trench sidewall silicon oxidation and to poly oxidation, i.e., "trench poly-fill". The oxygen diffusion results in volume expansion which in turn can lead to the introduction of stacking faults and dislocations through stress generation.
Another problem is that contaminants outdiffusing from a TEOS collar may contribute to interface problems between the two semiconductor fill layers within the trench. This can lead to severe contact problems of the trench electrode. An additional problem is that outdiffusion of dopants from the highly doped trench polysilicon fill through the collar is possible in the case of disrupted or otherwise damaged collars.
Accordingly, it is an object of the present invention to provide an improved trench cell capacitor for a DRAM which overcomes the problems of the prior art.
It is a further object of the instant invention to provide an improved isolation collar of a DRAM trench cell capacitor which has a nitride liner for avoiding the problems associated with prior art isolation collars.
It is yet another advantage of the present invention to provide improved processes for forming an isolation collar in a DRAM trench cell.
These and other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following detailed description of an exemplary embodiment thereof.